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PMC-Sierra, Inc. REFERENCE DESIGN
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PM3351 ELAN 1x100
2-PORT 10/100 MBIT/S ETHERNET SWITCH
PM3351 Elan 1x100
2-Port Fast Ethernet Switch Reference Design
PROPRIETARY AND CONFIDENTIAL
ADVANCE Issue 1: April , 1998
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PMC-Sierra, Inc. REFERENCE DESIGN
PMC-970390 ISSUE 1 ADVANCE
PM3351 ELAN 1x100
2-PORT 10/100 MBIT/S ETHERNET SWITCH
CONTENTS REFERENCES ....................................................................................................... ii OVERVIEW ........................................................................................................... 1 FUNCTIONAL DESCRIPTION .............................................................................. 2 Feature List ....................................................................................................2 PM3351 Elan 1x100 .......................................................................................4 IMPLEMENTATION DESCRIPTION ..................................................................... 6 100M Fast Ethernet Switch Circuitry ..............................................................7 Common Components .................................................................................10 Configuration Resistors ................................................................................12 Configuration Resistor Functions .................................................................14 INTERFACE DESCRIPTION............................................................................... 16 RJ45 Pin Definition.......................................................................................16 PCI Expansion Bus Interface .......................................................................17 LAYOUT DESCRIPTION..................................................................................... 20 Power and Ground Plane Isolation...............................................................20 Component Placement.................................................................................22 APPENDIX A: DESIGN CONSIDERATIONS ..................................................... 23 Power Supply Decoupling ............................................................................23 Unused CMOS Inputs ..................................................................................24 Additional Layout Considerations .................................................................24 Component Selection ...................................................................................26 APPENDIX B: BILL OF MATERIALS ................................................................. 28 CONTACTING PMC-SIERRA ............................................................................. 35 ATTACHMENT I: SCHEMATICS
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
REFERENCES * * * * * * * * PMC-Sierra PM3351 Datasheet, Issue 2 (July 1997) ISO/IEEE 8802.3 CSMA/CD Local Area Networking Specification (1993) IEEE 802.3u MAC Parameters, Physical Layer, Medium Attachment Units and Repeater for 100 Mbit/s Operation (January 1995) IEEE 802.3x Specification for 802.3 Full Duplex Operation (September 1996) National Semiconductor DP83840A Datasheet (1996) National Semiconductor DP83223 Datasheet (December 1996) National Semiconductor 100BASE-TX Unmanaged Repeater Design Recommendations (Appnote 1010) (October 1995) National Semiconductor 10/100 Ethernet Common Magnetics Using DP83840A and the DP83223 (April 1996)
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PM3351 ELAN 1x100
2-PORT 10/100 MBIT/S ETHERNET SWITCH
OVERVIEW This document describes an implementation of a 2-port Fast Ethernet Switch based on PMC-Sierra's PM3351 Elan 1x100 Standard Product. This reference design embodies PMC-Sierra's guidelines and suggestions for designing an Ethernet switch. This reference design is intended to operate in two modes: 1) Stand-alone mode, where this design provides the complete functionality of a 2-port Fast Ethernet Switch, and 2) This design can interface with other PMC switch reference designs through a PCI expansion backplane. It can be combined with the 24-port PM3350 ELAN 8x10 10Mbit/s Ethernet Switch reference design to form a 24+2 switch or another 2-port Fast Ethernet Switch Reference design to build a 4-port 100 Mbit/s switch. In addition to the PM3351 Elan 1x100 devices, this reference design incorporates onboard SRAM, EPROM, oscillators, 100BaseT PHY chips (National DP83840A, DP83223 chipset), 100BaseT magnetics, RJ45 jacks, status LEDs and other miscellaneous devices to complete the switch design. A complete list of components can be found in the Bill of Materials. The Functional Description gives a list of key features of this reference design. The Implementation Description provides a detailed description of all the major components which are found in the schematics (included as Attachment I). The Interface Description lists the RJ45 and the PCI expansion bus pin definitions. The Layout Description describes the component placement guidelines and general layout considerations. For readers who are interested more additional in-depth considerations for this reference design, the Design Consideration section provides many tips and guidelines for high-speed circuit board design and component selection. Finally, a Bill of Materials and the schematics are included at the end.
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PM3351 ELAN 1x100
2-PORT 10/100 MBIT/S ETHERNET SWITCH
FUNCTIONAL DESCRIPTION The block diagram of this reference design is shown in Figure 1. The following is a summary of the features offered in this switch. Feature List * * Complete 2-port full-duplex 100BASE-T non-blocking switching Operates i) as a completely stand-alone switch, or ii) in conjunction with other switch cards using the PCI expansion bus. It can be combined with the 24-port PM3350 ELAN 8x10 10Mbit/s Ethernet Switch reference design to form a 24+2 switch or another 2-port Fast Ethernet Reference design to build a 4-port 100 Mbit/s switch Supports a system bandwidth of 500 - 600 Mbit/s using the PCI expansion bus Filters and switches packets using a locally-maintained database1 Performs packet switching, IEEE 802.1d compliant transparent bridging, or both Store-and-forward mode with full CRC check.
* * * *
1 Refer to the System Configuration to determine the number of MAC addresses supported by the firmware programmed into the EPROM. The system can be configured to support up to 32k MAC addresses. See PM3351 datasheet.
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
Fig. 1 Reference Design System Block Diagram
System Clocks
PCI Expansion B us
E PRO M
Bus Arbiter
PM C 1x100 PM 3351
SR AM SR AM SR AM SR AM DP83840 10/100M PHY
PM C 1x100 PM 3351
SR AM DP83840 10/100M PHY SR AM SR AM SR AM
DP83223 100BAS E-TX Transceiver
DP83223 100BAS E-TX Transceiver
M agnetics
Status LEDs Status LEDs
M agnetics
RJ45
RJ45
Port 1
Port 2
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PM3351 ELAN 1x100
2-PORT 10/100 MBIT/S ETHERNET SWITCH
PM3351 Elan 1x100 Fig. 2 Block Diagram
50 MHz Embedded CPU
I Cache D Cache
PCI Expansion Bus
PCI Bus Interface
Transmit Channel Logic Receive DMA Controller
Tx FIFO Rx FIFO
100BaseT Transmit MAC 100BaseT Transmit MAC
100BaseT MII I/F
Expansion Registers
External memory Interface
SRAM / EPROM
PM3351 Overview The PM3351 is a low-cost, highly integrated stand-alone single-chip switching device for 10/100 Mbit/s Ethernet (IEEE 802.3u, IEEE 802.12) switching and bridging applications. The device supports all processing required for switching Ethernet packets between the on-chip Medium Independent Interface (MII) port and the built-in 1 Gbit/s expansion port, to which other PM3351 devices may be attached. In addition, the PM3351 is directly compatible with the PM3350, 8-port 10Mbps Ethernet switch chip. The PM3351 can be used with the PM3350 to create non-blocking switches of the configurations shown in the table below, with each 100 Mbit/s port configured for full-duplex and each 10 Mbit/s port configured for half-duplex All of the initialization, switching, interfacing, management and statistics gathering functions are performed by the PM3351, minimizing the size and cost of a switching
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
hub with one or more 100 Mbit/s ports. Switch configuration and management can be performed either remotely (in-band), via the on-chip SNMP MIB. The PM3351 chip contains all the required elements of a high-performance Ethernet switch: an MII interface for connection to physical-layer transceivers, MAC-layer processing logic, buffer FIFOs, a high-speed DMA engine for fast packet transfers, a local memory interface for up to 16 MB of external buffer memory, a fully-compatible PCI bus master and slave unit for modular expansion, and a powerful switch processing unit that implements the switching and bridging functions. The only additional components required for each 100 Mbit/s switch port are an MII compliant transceiver (supports 100BaseTX/FX, 100BaseT4,100BaseT2, and any future 802.3-compliant 100Mbit MII PHYs), passive line interface devices, a bank of external memory and a system clock. The amount of external memory may be extended up to 4 Mbytes pf SRAM, depending on the amount of packet buffering required and the number of MAC addresses to be supported. Switch configuration information is provided to the PM3351 using a single non-volatile device.
Table 1
Non-Blocking Configurations # PM3351 Devices 0 1 1 2 2 2 3 4 4 Switch Port Configuration 64x10 56x10 + 1x10/100 48x10 + 1x10/100 40x10 + 2x10/100 32x10 + 2x10/100 24x10 + 2x10/100 16x10 + 3x10/100 8x10 + 4x10/100 4x10/100
# PM3350 Devices 8 7 6 5 4 3 2 1 0
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PM3351 ELAN 1x100
2-PORT 10/100 MBIT/S ETHERNET SWITCH
IMPLEMENTATION DESCRIPTION The schematics of the 2-Port Elan 1x100 Reference Design, Revision D, are included in Attachment I. The core functionality consists of two identical2 "ports" or "slices" of 100M circuitry, each using a PM3351, SRAM memory, and physical interface components. Additionally, the board contains an EPROM for code download, PCI Arbiter, connectors, timing sources and miscellaneous "glue" circuitry. Functional blocks are described below. All of the major components are described for one slice of the 100M circuitry. The same description apply to both slices: * * Port 1: Sheets 3 - 5 Port 2: Sheets 6 - 8
The component ID's are listed in parenthesis after each component name.
Note that a component designated as PRES in the schematic indicates a signal either 1) pulled-up, 2) pulled-down, or 3) left unconnected (floating).
2Identical
except for the EPROM which only PM3351 #1 is connected to.
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
100M Fast Ethernet Switch Circuitry PM3351 U14 (SH3), U9 (SH6) The PM3351 Elan 1x100 chip forms the core of each slice of 100M switch circuitry. SRAM U11, U12, U21, U22 (SH4); U1, U2, U19, U20 (SH7) Four, 128K by 8-bit, 15ns SRAM chips (512K bytes total) are used to provide RAM storage for each PM3351. The SRAM is used for MAC address tables, packet buffer storage, and for data structures required during operation. EPROM U10 (SH2) The board uses a 256K x 8-bit EPROM for the PM3351 boot code, switching code, SNMP code (when available), and any special function code (e.g., custom LED display, aging, backpressure, VLAN, etc.). The EPROM must be 150 ns or faster. Code is downloaded into the first PM3351 device [U14], which in turn will download the code to the other PM3351 device [U9]. If an application code image does not include SNMP management, then a smaller 128K by 8-bit device is adequate. This device has a socket for ease of replacement. 10/100M Physical Layer Device U15 (SH5), U6 (SH8) The National Semiconductor DP83840A is a Physical Layer device for 10BASE-T and 100BASE-Tx Ethernet systems. It contains all the MAC layer functions, and it supports full-duplex operation. It features the Media Independent Interface (MII) which is used to connect to the PM3351 device, and it interfaces with the PMC sublayer through the DP83223 Twister Pair Transceiver. It comes in a 100-pin PQFP package.
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U15/U6 Configuration Interface:
SIGNAL NAME REQ
PIN #
DESCRIPTION
PCB REF
CONFIG
SETTING
29
Equalization Resistor
R83/R4
Open
Tx cable lengths < 100m Tx cable lengths < 100m Autonegotiation enabled Autonegotiation enabled
RTX
28
Extended Cable Resistor
R95/R3
Open
AN0
95
Operating Mode
R147/R67
Open
AN1
46
Operating Mode
R96/R7
Open
Please refer to a current issue of the National Semiconductor Databook for additional information describing this 10/100M physical layer device. Transceiver U17 (SH5), U7 (SH8) The National Semiconductor DP83223 TWISTER transceiver interfaces with up to 100 meters of 100 ohm UTP5 cable at 100M data rate. It is compliant with the ANSI X3T12 TP-PMD standard and the IEEE 802.3 100BASE-TX standard. It comes in a 28-pin PLCC package. Note that MLT-3 encoding is used (100BASE-TX). U17/U7 Configuration Interface:
SIGNAL NAME EQSEL
PIN #
DESCRIPTION
PCB REF
CONFIG
SETTING
17
Equalization Select
R151/R73
Open
Adaptive Equalization Mode
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
Please refer to a current issue of the National Semiconductor Databook for information describing this Twister Pair Transceiver device. Line Interface Circuitry The line interface circuitry consists of the transformers, connectors and passive networks necessary to interface the National DP83223A transceiver to cables carrying Ethernet 100 BaseT signals. This circuitry reflects recommendations in the National Semiconductor Databook and associated application notes. Please refer to the Design Considerations section for details on this circuitry. Transformers T1 (SH8), T2 (SH5) Single 100-BASE-TX transformers with common mode chokes are used in this reference design. Dual directional transformers are used to save space and cost, given that the crosstalk between the transmit and the receive is acceptable (better than 35dB). Please refer to the component selection section in Appendix A for vendor information. RJ45 Connectors J1 (SH8), J2 (SH5) There are two RJ45 connectors for connection of Ethernet 100 BaseT segments to the switch. Shielded RJ45 connectors are used to minimize electromagnetic interference (EMI). These connectors are configured as a "hub" connection. Please refer to the Interface Description section for details on pin definition. PHY Layer LEDs D8, D9, D10, D11, D12 (SH5); D1, D2, D3, D4, D5 (SH8); D6, D7 (SH4) There are five LEDs per port, arranged horizontally next to the featured port. They indicate status information as shown in the following table:
D1/D8
Full Duplex LED: Indicates Full Duplex mode status for 100 Mbit/s operation. Inacitve in Full Duplex 10 Mbit/s mode. Collision LED: Indicates the presence of collision activity for 10 Mbit/s and 100 Mbit/s operation. This LED has no meaning for Full Duplex operation. Receive LED: Indicates the presence of any receive activity.
D2/D9
D3/D10
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D4/D11 D5/D12
Transmit LED: Indicates the presence of transmit activity. Link LED: Indicates Good Link status.
Status LEDs D6, D7, D13-D26 (SH4/7) Status LEDs which can be used by the RISC controller to indicate system status. Common Components System Clocks U4, U8 (SH2) The system clock to the PM3351 devices is sourced from a 50 MHz crystal oscillator [U8]. A 74AC540 buffer [U5] is used to drive the clock signal to each chip. The PCI bus clock is sourced from a 40 MHz crystal oscillator [U4]. The 74AC540 is also used to drive the clock signal to each PM3351 and the arbiter. Both oscillators have sockets for ease of replacement. Sockets can be omitted to lower the cost of manufacturing. PCI Edge Connector Termination Resistors R164-R171 (SH3) This set of resistors pull-up the PCI control signals to ensure that they contain stable values when no agent is actively driving the bus. This includes FRAME, TRDY, IRDY, INTA, DEVSEL, STOP, SERR, and PERR. PCI Bus Connector P1 (SH2) This edge connector connects the onboard PCI bus to the expansion port backplane. It is used to interface this board to other reference designs such as the 24-port 10M Ethernet Switch using the PM3350. When this reference design is operating in the stand-alone mode, this edge connector is not used. Please refer to the Interface Description section for the pin definitions.
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Note that this PCI connection is not compliant to the PCI specification, v2.1. This is because of 1) the pin redefinition required for PCI arbitration (see the PCI Arbiter description), and 2) the fact that there are more than one "PCI device load" on a single board attached to the bus. PCI Arbiter U3 (SH2) A PCI Arbiter implements a simple round-robin algorithm to control bus access by the PM3351 devices onto the PCI expansion bus. This arbiter is implemented in a 44-PLCC CPLD (Xilinx XC9572). Please contact PMC-Sierra, Ethernet Division, for information on the implementation of the arbiter. This arbiter should be removed when this reference design board is interfaced to the 24-port 10M Ethernet Switch reference design. In this case, the PCI arbiter on the 24port reference design assumes control over the PCI bus. Because of this, additional REQ/GNT signals of the PM3351 devices are routed through the PCI bus backplane, which is accomplished by re-defining some of the unused pins on the PCI connector. This device has a socket for ease of replacement. Headers and Jumpers
JP1 (SH2) 1-2 3-4
PCI REQ0/1 Enable: If connected, the PM3351 PCI bus request appears at the PCI bus edge connector for processing by an external arbiter. This header is connected only when another reference design is connected to this board, and this board is configured as the slave board (i.e. the PCI arbiter is not populated, and the arbiter on the external board has control of the PCI bus). PCI GNT0/1 Enable: If connected, PCI grants received from an external arbiter over the PCI bus edge connector are enabled at the PM3351 interface. This header is connected only when another reference design is connected to this board, and this board is configured as the slave board (i.e. the PCI arbiter is not populated, and the arbiter on the external board has control of the PCI bus). PCI Clock Source: The clock may be sourced from the on-board oscillator [U4], or from the PCI bus edge connector [P1]. Connecting this header selects the on-board oscillator. Jumper the header when the board is being operated stand-alone, or if the board is the clock source for another reference design. Port 1 ERST Enable: Connect the header to implement the watchdog capability of the port 2 PM3351. A watchdog timeout will invoke a system reset.
JP2 (SH2) 1-2 3-4
JP3 (SH2)
JP6 (SH3)
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JP7 (SH2) JP8-2 (SH2) JP9-2 (SH2) JP10 (SH2)
PCI Reset Select: Jumper if the board is part of a multi-board system. PCI Clock Test Point System Clock Test Point PCI Control Signals Test Points: 1=GND, 2=FRAME, 3=IRDY, 4=TRDY, 5=DEVSEL, 6=GND. PM3351 U14 Debug Pins PM3351 U14 IDSEL: 1-2. Selects PCI Address bit 29. Jumper if (1) the board is used with a PM3350 reference board, or if (2) the board is part of a 4 PM3351 system and is designated as the slave/slave board. 2-3. Selects PCI Address bit 31. Jumper if the board is part of a 4 PM3351 system and is designated as the master/slave board.
JP11 (SH3) JP12 (SH3)
JP13 (SH4)
PCI RUN Bit Bank 0: 1-2. Jumper if PM3351 U14 (bank 0) is a slave device. 2-3. Jumper if PM3351 U14 (bank 0) is a master device.
JP14 (SH4)
PM3351 Reserved Bit: 1-2. Default
JP15 (SH4)
PM3351 U14 CHIPID1: 1-2. Jumper if PM3351 U14 is configured as a slave device. 2-3. Jumper if PM3351 U14 is configured as a master device.
JP16 (SH6) JP17 (SH6)
PM3351 U9 Debug Pins PM3351 U9 IDSEL: 1-2. Selects PCI Address bit 28. Jumper if (1) the board is used with a PM3350 reference board, or if (2) the board is part of a 4 PM3351 system and is designated as the slave/slave board. 2-3. Selects PCI Address bit 30. Jumper if the board is part of a 4 PM3351 system and is designated as the master/slave board, and is operated in standalone mode.
JP18 (SH7)
PM3351 U9 Reserved Bit: 1-2. Default.
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JP19 (SH7)
PM3351 U9 CHIPID1: 1-2. Jumper if PM3351 U9 is configured as a slave and U14 is also a slave. 2-3. Jumper if PM3351 U9 is configured as a slave and U14 is a master.
Reset Debounce Circuit U23 (SH2) The Dallas DS1233 "EconoReset" device is used to provide power-up reset and the reset debounce function. It monitors the status of the power supply (Vcc) and will automatically assert the reset when a threshold is crossed. Reset is maintained active for a minimum time of 350ms. Reset Switch SW1 (SH2) This switch is a master reset for the reference design board. Power Supply Connectors JK1, JK2 (SH9) This reference design board requires a 5.0V +/- 5% power supply capable of providing a minimum of 2.5 Amps. Configuration Resistors Each "slice" of 100M port circuitry uses a bank of 4.7K ohm resistors to configure the PM3351 after reset. The Configuration Resistors provide the default pull-up/down values on the local memory data bus, which are read by the PM3351 after reset. The resistor functions and default values are given below.
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Function PCIRUN RISCRUN Reserved IMDIS PCI3V FIRM CHIPID [3] CHIPID [2] CHIPID [1] CHIPID [0] RTCDIV [5] RTCDIV [4] RTCDIV [3] RTCDIV [2] RTCDIV [1] RTCDIV [0] MXSEL1 MXSEL0 MSLO MDCAS MTYPE3 [2] MTYPE3 [1] MTYPE3 [0] MTYPE2 [2] MTYPE2 [1] MTYPE2 [0] MTYPE1 [2] MTYPE1 [1] MTYPE1 [0] MTYPE0 [2] MTYPE0 [1] MTYPE0 [0]
Bank 0 R197 R172 R198 R199 R200 R201 R202 R203 R173 R204 R205 R206 R207 R208 R209 R210 R211 R212 R213 R214 R215 R216 R217 R218 R219 R220 R221 R222 R223 R224 R225 R226
Value 1 JP13 JP14 0 0 0 1 1 JP15 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0
Bank 1 R250 R251 R252 R253 R254 R255 R256 R257 R175 R258 R259 R260 R261 R262 R263 R264 R265 R266 R267 R268 R269 R270 R271 R272 R273 R274 R275 R276 R277 R278 R279 R280
Value 1 0 JP18 0 0 0 1 1 JP19 0 1 1 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0
Data Bus D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
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Configuration Word Functions PCIRUN: This input to the PM3351 selects the default operating mode of the PCI interface. If logic 1, the device responds to PCI memory space accesses and to be a bus master. If logic 0, the device is disabled from responding to PCI memory space accesses and will not be a bus master. RISCRUN: A logic 0 halts the Switch Processor upon reset, effectively placing the PM3351 into stand-by mode. IMDIS: Internal memory disable, which controls the bootcode fetch location. High = boot strapped from the external local memory, Low = boot strapped from on-chip ROM. PCI3V: This selects the PCI interface signaling environment. High = 3.3V, Low = 5V. CHIPID: These 4-bits determine the chip's PCI address. This is used to set the second nibble (bits 24 - 27) of the PM3351's address space on the PCI bus. The top nibble (bits 28 - 31) are initialized to zero (0), but can be set by software control if required. RTCDIV: These 6-bits determine the setting for the Real-Time Clock Divisor. MTYPE Configuration These twelve resistors per PM3351 are divided into four groups of three bits each. Each bit combination selects one of eight different memory types. These bits are read off the data bus during start-up, and tell the RISC how to access memory. Each group corresponds to one of the four banks of memory. On the reference design board: * * * * Bank 0 is configured as type SRAM, Bank 1 is configured as type EPROM (unused) Bank 2 is configured as type EPROM Bank 3 is configured as type EPROM (LED select)
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MTYPE 000 001 010 011 100 101 110 111 Reserved Reserved SRAM Reserved Reserved EPROM EDO DRAM
Memory Type
Speed n/a n/a 15 ns n/a n/a 150 ns 60 ns 60 ns
EDO DRAM/Fast Page DRAM
The memory configuration for this reference design is four 128K x 8bit, 15ns SRAM chips per PM3351.
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INTERFACE DESCRIPTION This section is a detailed description the physical interfaces in this reference design, which include 1) the RJ45 connectors, and 2) the PCI Expansion Bus connector. RJ45 Pin Definition Each of the two RJ45 connectors on the reference design have the following pin definition.
Signal Name TX+ TX RX + RX Pin 3 6 2 1 I Receive Pair on UTP5 Cable. Type O Description Transmit Pair on UTP5 Cable.
The pins are defined such that the port looks like a hub port. This allows a direct cable connection from the switch port to a computer. A crossover cable is needed to connect the switch port to another switch port.
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PCI Expansion Bus Interface
Signal Name AD[31:0] Pin B20 A20 B21 A22 B23 A23 B24 A25 B27 A28 B29 A29 B30 A31 B32 A32 A44 B45 A46 B47 A47 B48 A49 B52 Type I/O Description Multiplexed PCI address/data bus, used by the PCI host or the PM3351 to transfer addresses or data.
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B53 A54 B55 A55 B56 A57 A59 B58 CBE[3:0] B26 B33 B44 A52 PAR A43 I/O Address/data/command parity, supplies the even parity computed over the AD[31:0] and CBE[3:0] lines during valid data phases; it is sampled (when the PM3351 is acting as a target) or driven (when the PM3351 acts as an initiator) one clock edge after the respective data phase. Bus transaction delimiter (framing signal); a HIGH-to-LOW transition on this signal indicates that a new transaction is beginning (with an address phase); a LOW-to-HIGH transition indicates that the next valid data phase will end the currently ongoing transaction. Transaction Initiator (master) ready, used by the transaction initiator or bus master to indicate that it is ready for a data transfer. A valid data phase ends with data transfer when both IRDY* and TRDY* are sampled asserted on the same clock edge. Transaction Target ready, used by the transaction target or bus slave to indicate that it is ready for a data transfer. A valid data phase ends with data transfer when both IRDY* and TRDY* are sampled asserted on the same clock edge. Transaction termination request, driven by the current target or slave to abort, disconnect or retry the current transfer. I/O Command/Byte-Enable lines. These lines supply a command during the PCI address phase or byte enables during the data phase for each bus transaction.
FRAME*
A34
I/O
IRDY*
B35
I/O
TRDY*
A36
I/O
STOP*
A38
I/O
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DEVSEL*
B37
I/O
Device acknowledge: driven by a target to indicate to the initiator that the address placed on the AD[31:0] lines, together with the command on the CBE[3:0] lines, has been decoded and accepted as a valid reference to the target's address space. Once asserted, it is held asserted until FRAME* is de-asserted; otherwise, it indicates (in conjunction with STOP* and TRDY*) a target-abort. Device identification (slot) select. Assertion of IDSEL signals the PM3351 that it is being selected for a configuration space access. Bus requests. They are only used when the PCI expansion bus is used to interface with another board, such as the 24-port 10M Ethernet Reference Design. PCI 2.1 specification defines only one Bus Request signal. In this case, the extra Bus Request signals occupy the following unused pins on the PCI connector: B1: -12V (REQ1*), A1: TRST* (REQ0*)
IDSEL
A26
I
REQ* REQ1* REQ0*
B18 B1 A1
O
GNT* GNT1* GNT0*
A17 B7 A7
I
Bus grant from the bus arbiter; this indicates to the PM3351 that it has been granted control of the PCI bus. These are only used when the PCI expansion bus is used to interface with another board, such as the 24-port 10M Ethernet Reference Design. PCI 2.1 specification defines only one Bus Grant signal. In this case, the extra Bus Grant signals occupy the following unused pins on the PCI connector: B7: INTB* (GNT1*), A7: INTC* (GNT0*)
INT* PERR*
A6 B40
O I/O
Interrupt request. This pin signals an interrupt request to the PCI host. Bus parity error signal, asserted by the PM3351 as a bus slave, or sampled by the PM3351 as a bus master, to indicate a parity error on the AD[31:0] and CBE[3:0] lines. System error, used by the PM3351 to indicate to the PCI central resource that there was a parity error on the AD[31:0] and CBE[3:0] lines during an address phase. PCI bus clock; supplies the PCI bus clock signal to the PM3351. PCI bus reset (system reset). Performs a hardware reset of the PM3351 and associated peripherals when asserted.
SERR*
B42
OD
PCICLK RST*
B16 A15
I I
Note: * The '*' indicates active-low signals, which corresponds to '#' used in the PCI specification. * Pin numbers are listed MSB first
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LAYOUT DESCRIPTION Figure 5 shows the layout of this reference design. The purpose of this diagram is to show the Vcc and Ground plane isolation scheme in order to minimize noise-coupling between the various portions of the circuits, and EMI. This diagram shows only the approximate placement of the components. The layout is not meant to guarantee correct operation and performance of the design. In particular, PHY vendor recommendations should be consulted. Here, the power plane cuts are based on recommendations found in the National Semiconductor 100BASE-TX Unmanaged Repeater Design appnote (Appnote 1010, October 1995). Power and Ground Plane Isolation There are three islands of Vcc planes as shown in Fig. 5 for each "slice" of the 100M port circuitry. The Vcc plane cuts are to isolate 1) the Analog high-speed (125Mbps due to 4B/5B encoding) circuitry and traces for the DP83223 and the magnetics, 2) the high-speed (125M PECL due to 4B/5B encoding) digital circuitry and traces for the DP83223 and the DP83840A, and 3) the rest of the lower-speed (max. 50MHz) digital circuitry on the board. Power is fed into the Analog and PECL Vcc planes via ferrite beads (inductors). Important signals on the DP83223 and the DP83840A to be isolated to a specific Vcc plane are shown in the figure. These Vcc islands are on the same Vcc plane with minimum 50 mil separation between any two adjacent islands. There are two islands of Ground planes as shown for the entire board. The Ground plane cuts are to isolate the "cable" side from the "switch". Chassis ground covers the "cable" side of the magnetics and the RJ45 connector, whereas System ground covers the rest of the board. Chassis ground is used to provide a quiet ground plane for the UTP5 connection and to minimize EMI into and out of the RJ45 connection. A single System ground plane is used to minimize impedance, thus reducing ground noise. The System ground plane overlaps all Vcc islands, which minimizes fringing fields at the edges of the Vcc islands. To connect the chassis ground island to the system's chassis ground, the mounting screws can be used as chassis ground contact points as they make mechanical contact with the mounting bracket which in turn connects mechanically to the chassis. Furthermore, the shield of the RJ45 connector should be connected to the chassis ground island in order for it to be effective.
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Fig. 5 Board Layout
RJ45 Analog Vcc
DP 83223
RJ45 No Vcc Plane Analog Vcc
DP 83223
PECL Vcc
PECL Vcc
DP 83840
Digital Vcc
DP 83840 Common System Circuit ELAN 1x100 PM3351
Digital Vcc
ELAN 1x100 PM3351
PCI Bus Edge Connector
CT TDTD+
CT RDRD+
TXOTX+
PMIDPMID+
DP83223 Analog Vcc
SDSD+
PECL Vcc
Digital Vcc
DP83840
Digital Vcc
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Component Placement The overall placement strategies of the components are: * * * Place the analog circuitry away from the digital circuitry. Keep analog transmit side components (mostly passive) separate from the analog receive side components. Keep the transformer as close to the RJ45 as possible so that the commonmode noise riding on the traces coming from the RJ45 will be suppressed by the transformer before it can radiate. With adequate bypassing and decoupling on the digital side the digital Vcc and ground noise will not propagate to the analog section. Furthermore, additional filtering with ferrite beads on analog power supply reduces noise seen by the analog side, and attenuates noise generated by the analog side. Local decoupling capacitors are also placed near all analog and digital power supply pins.
*
In addition, the following guidelines are used: * * * All source termination resistors are placed near the outputs and load termination resistors are placed near the inputs. All pull down resistors are placed near the output pins. All decoupling capacitors are placed near the power supply pins. All bypassing capacitors on the analog side are placed near the ferrite beads. The bulk decoupling capacitors (22uF) are placed near the power entrance.
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APPENDIX A: DESIGN CONSIDERATIONS For those who are interested more additional in-depth considerations for this reference design, this Design Consideration section provides many tips and guidelines for highspeed circuit board design and component selection. Power Supply Decoupling Power pins Analog power supply pins on the DP83840A and DP83223 devices requires special attention to filter out Vcc noise. For the power pins on the PECL Vcc plane and the Analog Vcc plane, a 0.01uF or 0.1uF bypassing capacitor is placed near each power pin, together with 22uF bulk decoupling capacitors for the entire plane. A 0.01uF or 0.1uF decoupling capacitor is also placed as close to each digital power pin as possible. Ferrite beads are not used on the digital power pins because they add series inductance which limits the current that is required to recharge the decoupling capacitors. If noise attenuation is required, a small surface mount series resistor (1 to 10 ohms) can be added in series with the power pin. Fig. 6 Power Supply Decoupling
(place at close to pin as possible) Analog Vcc plane Analog power pin decoupling PECL power pin decoupling PECL Vcc plane (place at close to pin as possible) Digital Vcc plane (place at close to pin as possible) PECL Vcc plane Ferrite bead 0.01uF Digital Vcc Plane 22uF 0.01uF 22uF Analog power pin 0.01uF
PECL power pin 0.01uF Digital power pin 0.1uF Analog Vcc plane
Digital power pin decoupling Analog power plane decoupling
PECL power plane decoupling
Ferrite bead 22uF
PECL Vcc plane 0.01uF
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Power planes Analog circuitry draws mostly constant current and requires little switching current. Therefore, ferrite beads are used to isolate the Analog Vcc plane from the noisy PECL/Digital Vcc plane. Bulk decoupling is provided for the Digital Vcc islands. 22uF electrolytic capacitors are used for this purpose, and they are placed at the entrance of each Digital Vcc island. In addition, 22uF capacitors are placed after the ferrite bead that feeds power to the PECL Vcc islands. Please consult the National Semiconductor datasheets for more detail on power supply decoupling of the PHY devices. Unused CMOS Inputs "Floating" CMOS inputs (those that are left unconnected) may switch unpredictably, causing unwanted noise and power consumption. Therefore, all unused inputs should be connected to their inactive state: to ground or to the power rail. Unused bidirectionals should be "pulled" through a series resistor (4.7k or greater) to avoid shortcircuits occurring if the bi-directionals are erroneously configured as outputs. Additional Layout Considerations High-speed Traces High speed traces should be kept as short as possible in general. This applies to the traces with high-speed data between the RJ45 connector, the magnetics and the DP83223, which carry 125Mbps data (125 Mbit/s is due to the 4B/5B encoding). These traces should be treated as transmission lines, with proper terminations applied (please refer to the schematics for terminations. Also please consult the PHY device vendor datasheets for recommendations on proper termination). In addition, the pair of traces for the differential signals should have the same length, so as to minimize signal distortion and jitter. The traces with the high-speed data between the RJ45 connector, the magnetics and the DP83223 should have an impedance of 50ohm, in order to match the 100ohm differential impedance of the UTP5 cable. Controlled impedance traces can be used to ensure a 50ohm impedance. EMI Considerations EMI can be reduced via proper routing, decoupling, power and ground distribution, shielding, and filtering. Most of the items listed below for EMI improvement also lend themselves towards improving system level performance.
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Routing Guidelines Proper decoupling and termination are effective ways of reducing EMI. The following are some routing guidelines which will help reduce EMI: * * Data lines should be kept away from the clock signals to avoid noise coupling. No high speed signals should be routed near the vicinity of the RJ45 modular jack and the transformer in order to prevent common-mode noise coupling onto the cable. Footprints of capacitors can be placed along signals with fast rise and fall times. In the event that fast edges causes excessive EMI, they can be slowed down (if timing and system level performance are not compromised) using these capacitors.
*
Power and Ground planes * * The power plane should be kept away from the RJ45 modular jack and the transformer to prevent noise coupling. When separate power planes are used, keep the power planes away from each other. Ensure that for each section of the power plane, there is a ground plane of larger size underneath. The larger ground plane, plus the physical separation of the power planes, will reduce the return current or noise from fringing into adjacent planes. Power planes should also be kept away from the edge of the board to prevent noise fringing between the power and ground planes at the edge of the card and causing unwanted emission. Ensure that power and ground planes of different sections do not overlap in order to prevent noise coupling. Provide a chassis ground plane under the RJ45 modular jack.
* *
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Component Selection SRAM The following table shows a selection of compatible SRAM's that can be used in this design:
Vendor Toshiba Hitachi IDT
Configuration 128K x 8 128K x 8 128K x 8
Part Number TC558128AJ-15 HM628127HBJP-15 IDT71024S15Y
Package 32SOJ 32SOJ 32SOJ
RJ45 Connector 8-pin 8 position RJ45 modular jacks are used in this reference design. There are three types of modular jacks: * * * non-filtered and non-shielded shielded and non-filtered shielded and filtered (capacitive filtering or inductive filtering)
A shielded and non-filtered jack is used in the reference design. Furthermore, in order for the shielding to be effective, the shield should be electrically connected to the chassis ground via a low impedance connection (i.e. using copper finger stocks or firm mechanical contact with the mounting bracket). Typically, the shielded portion of the jack will extend through the opening in the mounting bracket and make firm mechanical contact with the bracket on all sides. The following vendors provide RJ45 connectors: * * * Stewart Connectors AMP Kycon Tel: 717-235-7512 Tel: 800-522-6752 Tel: 800-544-6941
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*
Power Dynamics
Tel: 201-736-5722
Transformer The following transformers are recommended: * * Pulse Engineering PE68515 Valor PT4171S Tel: 619-674-8100 Tel: 800-318-2567
Both have chokes built-in. They are pin-compatible. PE68515 is selected because of better overall performance. Oscillator The on-board oscillators provide a timing reference for the PM3351 device, the National PHY chipset, and the PCI bus interface. The oscillators should be +/-100ppm or better. The stability figure of an oscillator should include any variation due to calibration, temperature, voltage, load, aging, shock, and vibration, and is specified over the lift time of the oscillator. Either CMOS or TTL oscillator can be used. The following is a list of vendors that provide these oscillators: * * * * * Motron Industries Connor Winfield Champion Oak Frequency Control Group Ecliptek Tel: 605-665-9321 Tel: 708-851-4722 Tel: 708-451-1000 Tel: 717-486-3411 Tel: 714-433-1200
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APPENDIX B: BILL OF MATERIALS This table lists the components used in this reference design. Note that compatible components can be substituted, but this is not guaranteed. Please refer to the Component Selection section in Appendix A for suggestions on alternative sources for some of the major components.
Item 1 Board ID Description Mfgr Panasonic Part Number ECU-V1H104KBW Qty 105
0.1 uF surface mount C1, C2, C3, C4, bypass capacitor, 1206 C5, C6, C9, C10, SMD package C11, C16, C23, C24, C26, C27, C28, C29, C30, C31, C32, C35, C36, C37, C38, C40, C41, C42, C43, C44, C45, C47, C51, C56, C57, C58, C59, C60, C61, C62, C63, C64, C65, C68, C69, C70, C71, C72, C73, C74, C75, C76, C78, C80, C81, C82, C83, C84, C85, C87, C88, C89, C90, C91, C99, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109, C112, C113, C115, C116, C117, C118, C121, C122, C124, C125, C126, C127, C128, C129, C130, C132, C138, C139, C142, C146, C149, C150,C155, C156, C157, C158, C159, C160, C161, C162, C163, C164
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2
C7, C8, C25, C46, 22 uF surface mount bypass capacitor EIA Size C50, C52, C53, C C54, C66, C79, C86, C93, C131, C135, C140, C141, C145, C147, C151, C152, C153, C154, C165, C166
Panasonic
ECS-T1AC226R
24
3
0.01uF multi-layer ceramic Panasonic C12, C15, C19, chip capacitor, 1206 SMD C20, C22, C33, package C34, C39, C48, C49, C55, C67, C77, C92, C96, C110, C114, C119, C120, C133, C134, C136, C137, C148 C13, C14, C17, C94, C95, C98 1000 pF multi-layer ceramic chip capacitor, 0805 SMD package 9 pF multi-layer ceramic chip 0805 SMD package Panasonic
ECU-V1H103KBM
24
4
ECU-V1H102KBM
6
5
C18, C97
Panasonic
ECU-V1H090DCN
2
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Item 6
Board ID C21, C111
Description 0.001 uF 2KV ceramic disc capacitor 500 pF 1206 SMD 10 uF EIA Size B
Mfgr Panasonic
Part Number ECK-D3D102KBP
Qty 2
7 8 9
C123 C143, C144
1 2 26
LED D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26 FB1, FB2, FB3, FB4, FB5, FB6, FB7, FB8 JP1, JP2 Ferrite Bead 1206 SMD package Murata BLM31A700SPTM03
10
8
11
4 pin double row header 0.100 inch spacing 2 pin single row header 0.100 inch spacing Header 6 Header 3
Sullins
PZC04DACN
2
12
JP3, JP6, JP7, JP8, JP9 JP10 JP11, JP12, JP13, JP14, JP15, JP16, JP17, JP18, JP19 J1, J2
Sullins
PZC02SACN
3
12.1 12.2
1 9
13
Single RJ45 jack with shield, 8 position NPN transistor SOT-23 package
AMP
558505-1
2
14
Q1, Q2, Q3, Q4, Q5, Q6 -------------------------------------------
National
MMBT2222A
6
15 16
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Item 17
Board ID R1, R2, R3, R4, R5, R7, R8, R10, R13, R15, R16, R20, R21, R24, R25, R34, R44, R45, R57, R63, R64, R67, R68, R70, R71, R73, R76, R77, R78, R79, R83, R86, R87, R90, R95, R96, R97, R99, R102, R106, R107, R109, R111, R113, R116, R124, R133, R138, R147, R148, R149, R151, R153, R154, R155, R156, R157, R164, R165, R166, R167, R168, R169, R170, R172, R173, R175, R176, R177, R178, R179, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R289, R290 R9, R14, R17, R23, R27, R30, R103, R108, R112, R118, R121, R128
Description 4.7K ohm, 5%, 0.1W chip resistor 0805 SMD package
Mfgr Panasonic
Part Number ERJ-6GEYJ4.7K
Qty 134
18
51 ohm, 0805 SMD
12
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19
R6, R11, R12, R19, R33, R50, R98, R100, R101, R105, R123, R130 R18, R22, R104, R110
10 ohm, 0805 SMD
12
20
47 ohm, 0805 SMD
4
Item 21
Board ID R26, R36, R47, R55, R61, R65, R119, R122, R127, R139, R141, R144 R28, R31, R115, R120 R29, R32, R51, R53, R56, R66, R117, R125, R131, R140, R143, R145 R35, R48, R126, R132
Description 82 ohm, 0805 SMD
Mfgr
Part Number
Qty 12
22
39 ohm, 0805 SMD
4
23
130 ohm, 0805 SMD
12
24
75 ohm, 0805 SMD
Panasonic
ERJ-6ENF75
4
25
R38,R40, R41, R42, 22 ohm, 0805 SMD R43, R46, R58, R81, R84, R85, R88, R89, R91, R93, R94, R136, R162, R163, R174, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249 R49, R129 511 ohm, 0805 SMD
24
26
2
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R52, R54, R62, R69, R72, R137, R142, R146, R150, R158 R59, R92, R135 R74, R152 R80, R82, R227, R228, R229, R230, R231, R232, R281, R282, R283, R284, R285, R286, R287, R288 R171 SW1 T1, T2
680 ohm, 0805 SMD
10
28 29 30
1.0K ohm, 0805 SMD 3.9 ohm, 0805 SMD 390 ohm, 0805 SMD
5 2 2
31 32 33
2.7K ohm, 0805 SMD Pushbutton SW Panasonic EVQ-QEC05K PE-68515L
1 1 2
10/100M LAN Transformer Pulse Engineering
34
U1, U2, U11, U12, 128K x 8 SRAM, 32SOJ U19, U20, U21, U22 U3 U4 CPLD 40.0 MHz TTL Clock Oscillator 8 pin DIP 50.0 MHz TTL Clock Oscillator 8 pin DIP Inverting Tri-State Buffer
Hitachi
HM628127HBJP-15
8
35 36
XILINX Epson America
XC9572-15 SG-531PH40.000MC SG-531PH50.000MC 74AC540 DP83840AVCE
1 1
37
U8
Epson America
1
38 39
U5 U6, U15
National Semi
1 2
10/100M Ethernet Physical National Semi Layer 100 pin PQFP
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Line 40
Board ID U7, U17
Description 100BASE-TX Transceiver 28 PLCC
Mfgr National
Part Number DP83223VCE
Qty 2
41
U9, U14
Fast Ethernet Switch IC metal package EPROM, 1M bit; 256K x 8 32DIP package
PMC-Sierra
PM3351
2
42
U10
AMD
AM27C020 -150DC
1
43 44
U13, U24 U18
Octal D Flip-Flop 3.3 V Regulator, 4.6 A
National Semi Linear Technology Dallas E.F. Johnson E.F. Johnson
74AC825SC LT1585CT-3.3
1 1
45 46 47
U23 JK1 JK2
Econo Reset Banana jacks - red Banana jacks - black
DS1233 111-0102-001 111-0103-001
1 1 1
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E L A N 1 x1 0 0 : 2 P ort 1 0 /1 0 0 M bit/s S w itch
Physical Layer Port 1 Sheet 5
SRAM, Config Resistors, LED's Sheet 4 Clocks, PCIBus, EPROM Sheet 2
PM3351 Port 1 Sheet 3
PM3351 Port 2 Bypass caps, Regulator Sheet 9 SRAM, Config Resistors, LED's Sheet 7 Sheet 6
Physical Layer Port 2 Sheet 8
P M C - S ie rra , Inc.
Tit le
E the rne t D ivisio n
P ortland, OR. U.S .A . P M 3351 2 P ort Ref. Design - TOP
S ize A D at e: D oc u m ent N u m ber Mond ay , N ov e m ber 03, 1997 S heet 1 of 9 R ev
D
PCI A RBITER VCC 28 R176 R177 R178 R179 R10 R1 R2 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 7 8 9 11 12 13 14 15 16 27 26 25 24 22 20 19 18 17 2 4 I/FI I/FO/FI I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO/FI I/FO/FI I/FO/FI I/FO U3 XC9572 I/FI I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO FO/FO E1 FO/FO E0 I/FO/FI I/FO/FI I/FO/FI/MR I/FO/FI I/FO/FI I/FO/FI FO/CLK0 FO/CLK1 42 29 30 33 34 35 36 37 38 39 40 43 44 1 2 3 4 5 6 VCC FRAME GNT _0 GNT _1 JP2 1 3 2 4 A17_0 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 30 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12 U10 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 27C020
D7 D6 D5 D4 D3 D2 D1 D0
21 20 19 18 17 15 14 13
D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0 CS2_0 RD_0
REQ_0 REQ_1
RESET
22 CE 24 OE
JP1 1 3
PCICLK_2
CBE2 FRAME
DEVSEL ST OP
SERR PAR
AD15 CBE1
PERR
JP3 INT A AD30 AD31 AD29 AD28 AD26 AD27 AD25 AD24 AD23 AD22 AD20 AD21 AD19 AD18 AD16 AD17 JP7 PCI CLOCK SELECT 1 2 1 2 CBE3
AD10 AD9
CBE0 AD8
AD7 AD6
AD4 AD5
AD3 AD2
IRDY T RDY
AD14 AD13
AD11 AD12
AD0 AD1
VCC
P1 PCI_CONN
1 2
U5 40 MHZ PCI BUS CLOCK U4 5 R38 22 CLK 5 2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 74AC540 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 R37 R39 R159 R160 R161 R180
61.9 61.9 61.9 61.9 61.9 22
1 2
1 2
C123 500PF
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 A11 B11 A12 B12 A13 B13 A14 B14 A15 B15 A16 B16 A17 B17 A18 B18 A19 B19 A20 B20 A21 B21 A22 B22 A23 B23 A24 B24 A25 B25 A26 B26 A27 B27 A28 B28 A29 B29 A30 B30 A31 B31 A32 B32 A33 B33 A34 B34 A35 B35 A36 B36 A37 B37 A38 B38 A39 B39 A40 B40 A41 B41 A42 B42 A43 B43 A44 B44 A45 B45 A46 B46 A47 B47 A48 B48 A49 B49 A50 B50 A51 B51 A52 B52 A53 B53 A54 B54 A55 B55 A56 B56 A57 B57 A58 B58 A59 B59 A60 B60 A61 B61 A62 B62 50 MHZ SYSTEM CLOCK U8 SY SCLK_0 SY SCLK_1 PCICLK_0 PCICLK_1 PCICLK_2 RESET JP6 PHY_RESET VCC VCC JP8 JP9 PCICLK_0 SY SCLK_0 C151 22uF C152 22uF C153 22uF C154 22uF CLK R135 1.0K ERST 2 RESET U23 SW1 Manual Reset T itle DS1233
P M C- Sierra, Inc.
P ortlan d, OR. U.S.A.
E thernet Division
P M 335 1 2 P ort Ref. De sign - Bus, A rbiter, S ysClk, EPROM
Size B Date: Document Number Monday, November 03, 1997 Sheet 2 of 9 Rev
D
A17_0 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 D31_0 D30_0 D29_0 D28_0 D27_0 D26_0 D25_0 D24_0 D23_0 D22_0 D21_0 D20_0 D19_0 D18_0 D17_0 D16_0 D15_0 D14_0 D13_0 D12_0 D11_0 D10_0 D9_0 D8_0 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0 WR3_0 WR2_0 WR1_0 WR0_0 RD_0 CS3_0 CS2_0 CS0_0 MEMCLK_0 VP
R162 R163 R181 R182 R183 R184 R185 R186 R187 R188 R189 R190 R191 R192 R193 R194 R195 R196
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
114 115 116 117 119 120 121 122 125 126 127 128 129 130 135 136 137 138 159 160 161 162 164 165 166 167 170 171 172 173 174 175 176 177 178 181 182 185 186 187 188 189 192 193 194 195 196 197 200 201
MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MWR3 MWR2 MWR1 MWR0 MGWE MRD MRAS MCS3 MCS2 MCS1 MCS0 MEMCLK MINT R IDSEL CBE3 CBE1 AD30 AD31 AD29 AD28 AD26 AD27 AD25 AD24 AD23 AD22 AD20 AD21 AD19 AD18 AD16 AD17 AD15 AD14 AD13 AD11 AD12 AD10 AD9 CBE0 MRDY CBE2 FRAME IRDY T RDY DEVSEL ST OP PERR SERR PAR INT RST PCICLK GNT REQ
T X_CLK T XD3 T XD2 T XD1 T XD0 T X_EN CRS COL RX_CLK RX_ER RX_DV RXD3 RXD2 RXD1 RXD0 MDC MDIO ERST
100 109 108 107 102 101 111 110 97 98 96 92 93 94 95 88 83 89
T XCLK_0 T XD3_0 T XD2_0 T XD1_0 T XD0_0 T XEN_0 CRS_0 COL_0 RXCLK_0 RXER_0 RXDV_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 MDC_0 MDIO_0 ERST
JP10
1 2 3 4 5 6
VCC INT A FRAME IRDY T RDY DEVSEL ST OP PERR 1 R164 1 R165 1 R166 1 R167 1 R168 1 R169 1 R170 1 R171 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 4.7K 2 4.7K 2 4.7K 2 4.7K 2 4.7K 2 4.7K 2 4.7K 2 2.7K
nc nc nc nc
82 204 205 206 VP
JP11 1 2 3
SERR
U14 PM3351
T ST BIAS5V BIAS5V
203 103 1
R86
4.7K
VCC
R88 R85 R84 R81 R89 R94 R93 R91 R136 R87 R90
22 22 22 22 22 22 22 22 22 4.7K 4.7K
147 148 151 152 153 146 154 139 140 141 144 76 202 145
CLK25 SY SCLK AD8 AD7 AD6 AD4 AD5 AD3 AD2 AD0 AD1
81 78 SY SCLK_0
4 3 5 6 10 9 11 12
39 59 60 38 37
18 13
35 16 20 19 17 55 56 57 58
52
43 44 46 45 49 50
75
23 24 26 25 27 28 34 33
42
51 63 64 68 67 69 70 74 73
P M C- Sierra, Inc.
T itle Size B Date:
E thernet Division
REQ_0 GNT _0 PCICLK_0 RESET INT A
AD24 AD25 AD27 AD26 AD28 AD29 AD31 AD30 AD31 AD29
CBE3 R92
AD17 AD16 AD18 AD19 AD21 AD20 AD22 AD23 1.0K
PAR SERR PERR ST OP DEVSEL T RDY IRDY FRAME CBE2 JP12 3 2 1
AD15
CBE1
AD9 AD10 AD12 AD11 AD13 AD14
CBE0
AD1 AD0 AD2 AD3 AD5 AD4 AD6 AD7 AD8
P ortl an d, OR. U.S.A. PM 33 51 2 Po rt Ref. Desig n - PM 3 351 P ort 0
Document Number Monday, November 03, 1997 Sheet 3 of 9 Rev
D
SRAM
U11 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 13 14 15 16 17 18 19 20 21 29 30 31 32 1 2 3 4 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128KX8 D7 D6 D5 D4 D3 D2 D1 D0 27 26 23 22 11 10 7 6 D31_0 D30_0 D29_0 D28_0 D27_0 D26_0 D25_0 D24_0 CS0_0 RD_0 WR3_0 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 13 14 15 16 17 18 19 20 21 29 30 31 32 1 2 3 4 U21 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128KX8 JP13 U22 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 13 14 15 16 17 18 19 20 21 29 30 31 32 1 2 3 4 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128KX8 D7 D6 D5 D4 D3 D2 D1 D0 27 26 23 22 11 10 7 6 D23_0 D22_0 D21_0 D20_0 D19_0 D18_0 D17_0 D16_0 CS0_0 RD_0 WR2_0 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 13 14 15 16 17 18 19 20 21 29 30 31 32 1 2 3 4 U12 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128KX8 D7 D6 D5 D4 D3 D2 D1 D0 27 26 23 22 11 10 7 6 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0 CS0_0 RD_0 WR0_0 3 2 1 JP14 3 2 1 JP15 3 2 1 D7 D6 D5 D4 D3 D2 D1 D0 27 26 23 22 11 10 7 6 D15_0 D14_0 D13_0 D12_0 D11_0 D10_0 D9_0 D8_0 CS0_0 RD_0 WR1_0
5 CS 28 OE WE 12
5 CS 28 OE WE 12
Configuration Resisto rs
VCC VCC R197 R172 R198 R199 R200 R201 R202 R203 R173 R204 R205 R206 R207 R208 R209 R210 R211 R212 R213 R214 R215 R216 R217 R218 R219 R220 R221 R222 R223 R224 R225 R226 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K D31_0 D30_0 D29_0 D28_0 D27_0 D26_0 D25_0 D24_0 D23_0 D22_0 D21_0 D20_0 D19_0 D18_0 D17_0 D16_0 D15_0 D14_0 D13_0 D12_0 D11_0 D10_0 D9_0 D8_0 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0
5 CS 28 OE WE 12
5 CS 28 OE WE 12
VCC
R227 R228 U13 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0 CS3_0 MEMCLK_0 RESET 10 9 8 7 6 5 4 3 14 13 11 D8 D7 D6 D5 D4 D3 D2 D1 CLKEN CLK CLR 74AC825SC Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 15 16 17 18 19 20 21 22 R229 R230 R231 R232 R80 R82
390R 390R 390R 390R 390R 390R 390R 390R
D13 D14 D15 D16 D17 D18 D6 D7
23 O C3 2 O C2 1 O C1
P M C- Sierra, Inc.
T itle
E thernet Division
Portlan d, OR. U.S.A. PM3 351 2 Po rt Ref. Design - Memory 0
Size B Date: Document Number Monday, November 03, 1997 Sheet 4 of 9 Rev
D
VCC 38.3 38.3 VCC R115 VPECL_0 61 60 69 80 85 83 14 13 97 40 52 71 59 68 79 84 96 39 51 70 C112 .1uF C115 .1uF T2 PE68515 R144 R141 R127 R139 R119 R122 25 24 20 21 15 16 130 130 130 130 130 130 2 RXI+ 1 RXIR123 R130 10.5 10.5 Receive 1 Common Mode 2 Choke 3 16 14 15 Isolation Xformer 7 5 6 R120 C110 .01uF
4.7K
4.7K
4.7K
4.7K
4.7K
NC NC NC
RCLKGND IOGND4 IOGND5 IOGND6 REFGND
IOGND1 IOGND2 IOGND3 PCSGND
IOVCC4 IOVCC5 IOVCC6 REFVCC
IOVCC1 IOVCC2 IOVCC3 PCSVCC
4.7K
R97
R99
R133
R138
R106
R102
T XCLK_0 T XD3_0 T XD2_0 T XD1_0 T XD0_0 T XEN_0 CRS_0 COL_0 RXCLK_0 RXER_0 RXDV_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 MDC_0 MDIO_0 R147 R96 R107 R155 R154 R153 R149 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
82 75 76 77 78 74 73 66 65 62 63 64 55 56 57 58 43 72 67 95 46 47 98 99 100 1 86 81 2 34 33
T X_CLK MII T XD3 T XD2 INTERFACE T XD1 T XD0 T X_EN T X_ER CRS/PHYAD2 COL RX_CLK RX_ER/PHYAD4 RX_DV RXD3 RXD2 RXD1 RXD0 RXEN MDC MDIO AN0 CFG INTERFACE AN1 REPEAT ER 10BT SER BPALIGN BP4B5B BPSCR REFIN CLK25M CLOCK OSCIN INTERFACE X2 X1
100 Mb/s INTERFACE U15 DP83840A 10/100Mb/s ETHERNET PHY
RD+ RDSD+ SDT D+ T DLBEN/PHYAD0 ENCSEL/PHYAD1 RXI+ RXIT XU+ T XUT XS+ T XSREQ RT X
5 6 8 7 17 16 49 53 21 20 26 25 24 23 29 28
R111
4.7K
82.5
82.5
82.5
82.5
82.5
82.5
PMID+ PMIDSD+ SDU17 PMRD+ PMRDDP83223 TWISTER
9 T XO+ 8 T XO14 GND 22 GND 3 RXGND 28 RXGND 7 T XGND 10 T XGND 4 RXVCC 27 RXVCC 5 T XVCC 11 T XVCC C92 .01uF
Isolation Xformer
Common Mode Choke Transmit
Auto Xformer
10 12 11
10 Mb/s INTERFACE
4.7K R143 R131 R117 R145 R140 R125
R151
17 19 12 18 6
EQSEL LBEN ENCSEL CDET T XREF EXT VCC VCC VCC C98 1000pF 10.5 1000pF 10.5
R83 R95
4.7K 4.7K VCC VCC
JTAG INTERFACE
50 T D0 91 T D1 92 T RST 93 T CLK 94 T MS LED1 LED2 LED3 LED4 LED5 42 41 38 37 36
R157
4.7K R150 R146 R158 R137 R142 680 D11 680 D10 680 D12 680 D8 680 D9 LED LED LED LED LED 1%
23 13 26
J2 RJ45S-X2
LED INTERFACE
R105 C95 R101
SY SCLK_0
VCC R113 4.7K
Place Close To Pin !!!
CGMGND CRMGND ANAGND
CRMVCC ECLVCC CGMVCC
RES_0(4) RES_0(3) RES_0(2) RES_0(1)
ANAVCC PLLVCC
OGND PLLGND T DGND RXGND
OVCC T DVCC RXVCC
R148 R156 4.7K 4.7K
R124
4.7K
Q5 NPN
Q4 NPN
R104
1000pF R112 R103
50
50
VCC 9pF 9 31 4 45 90 48 35 30 27 19 12 15 87 32 22 18 88 11 10 75 R116 VPECL_0 R109 4.7K 4.7K C97 75
R108
R118
50
50
R289 4.7K
R110
Q6 NPN
R100 10.5
C94
Chassis Ground 50 50
R126
R132
R128
VCC 1
Ferrite Bead FB8 2 R152 4 C148 C147 .01uF 22uF
VCC
Ferrite Bead FB7 1 2 C137 C120 C118 C139 .1uF C138 .1uF C140 22uF C141 22uF .01uF .01uF .1uF 1
Ferrite Bead FB6 2 C133
VA_0 C119 C117 .1uF C116 .1uF C135 22uF C111 .001uF 2KV
.01uF .01uF
VCC
Ferrite Bead FB5 1 2 R98 10 C96 C93 .01uF 22uF
P M C- Sierra, Inc.
T itle
Portlan d, OR. U.S.A. PM3351 2 Port Ref. Design - Phy 0
Size B D Document Number Md N b 03 199 Sh f 9 Rev
R121
E thernet Division
SHIELD2 SHIELD1
54 SPEED_10 89 SPD_100/PHYAD3 44 RESET 3 LOWPWR
VCC PHY_RESET
47.5
R129 511
1 2 3 4 5 6 7 8
RD+ RDT D+ T D-
47.5
D
A16_1 A15_1 A14_1 A13_1 A12_1 A11_1 A10_1 A9_1 A8_1 A7_1 A6_1 A5_1 A4_1 A3_1 A2_1 A1_1 A0_1 D31_1 D30_1 D29_1 D28_1 D27_1 D26_1 D25_1 D24_1 D23_1 D22_1 D21_1 D20_1 D19_1 D18_1 D17_1 D16_1 D15_1 D14_1 D13_1 D12_1 D11_1 D10_1 D9_1 D8_1 D7_1 D6_1 D5_1 D4_1 D3_1 D2_1 D1_1 D0_1 WR3_1 WR2_1 WR1_1 WR0_1 RD_1 CS3_1 CS0_1 MEMCLK_1 VP
R174 R233 R234 R235 R236 R237 R238 R239 R240 R241 R242 R243 R244 R245 R246 R247 R248
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
114 115 116 117 119 120 121 122 125 126 127 128 129 130 135 136 137 138 159 160 161 162 164 165 166 167 170 171 172 173 174 175 176 177 178 181 182 185 186 187 188 189 192 193 194 195 196 197 200 201
MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MWR3 MWR2 MWR1 MWR0 MGWE MRD MRAS MCS3 MCS2 MCS1 MCS0 MEMCLK MINT R IDSEL CBE3 CBE1 AD30 AD31 AD29 AD28 AD26 AD27 AD25 AD24 AD23 AD22 AD20 AD21 AD19 AD18 AD16 AD17 AD15 AD14 AD13 AD11 AD12 AD10 AD9 CBE0 MRDY CBE2 FRAME IRDY T RDY DEVSEL ST OP PERR SERR PAR INT RST PCICLK GNT REQ
T X_CLK T XD3 T XD2 T XD1 T XD0 T X_EN CRS COL RX_CLK RX_ER RX_DV RXD3 RXD2 RXD1 RXD0 MDC MDIO ERST
100 109 108 107 102 101 111 110 97 98 96 92 93 94 95 88 83 89
TX CLK_1 TX D3_1 TX D2_1 TX D1_1 TX D0_1 T XEN_1 CRS_1 COL_1 RXCLK_1 RXER_1 RXDV_1 RXD3_1 RXD2_1 RXD1_1 RXD0_1 MDC_1 MDIO_1 ERST
nc nc nc nc
82 204 205 206 VP
JP16 1 2 3
U9 PM3351
T ST BIAS5V BIAS5V
203 103 1
R45
4.7K VCC
R43 R42 R41 R40 R46 R249 R58 R291 R44 R57
22 22 22 22 22 22 22 22 4.7K 4.7K
147 148 151 152 153 146 154 139 140 141 144 76 202 145
CLK25 SYSCLK AD8 AD7 AD6 AD4 AD5 AD3 AD2 AD0 AD1
81 78 SY SCLK_1
4 3 5 6 10 9 11 12
39 59 60 38 37
18 13
35 16 20 19 17 55 56 57 58
52
43 44 46 45 49 50
75
23 24 26 25 27 28 34 33
42
51 63 64 68 67 69 70 74 73
P M C- Sierra, Inc.
T itle Size B Date:
E thernet Division
REQ_1 GNT _1 PCICLK_1 RESET INT A
AD24 AD25 AD27 AD26 AD28 AD29 AD31 AD30 AD30 AD28
CBE3
AD17 AD16 AD18 AD19 AD21 AD20 AD22 AD23 R59 1.0K
PAR SERR PERR ST OP DEVSEL T RDY IRDY FRAME CBE2 JP17 3 2 1
AD15
CBE1
AD9 AD10 AD12 AD11 AD13 AD14
CBE0
AD1 AD0 AD2 AD3 AD5 AD4 AD6 AD7 AD8
Portland, OR. U.S.A. PM 3351 2 Port Ref. Design - Fed 1
Document Number Monday, November 03, 1997 Sheet 6 of 9 Rev
D
SRAM
U19 A16_1 A15_1 A14_1 A13_1 A12_1 A11_1 A10_1 A9_1 A8_1 A7_1 A6_1 A5_1 A4_1 A3_1 A2_1 A1_1 A0_1 13 14 15 16 17 18 19 20 21 29 30 31 32 1 2 3 4 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128KX8 D7 D6 D5 D4 D3 D2 D1 D0 27 26 23 22 11 10 7 6 D31_1 D30_1 D29_1 D28_1 D27_1 D26_1 D25_1 D24_1 CS0_1 RD_1 WR3_1 A16_1 A15_1 A14_1 A13_1 A12_1 A11_1 A10_1 A9_1 A8_1 A7_1 A6_1 A5_1 A4_1 A3_1 A2_1 A1_1 A0_1 13 14 15 16 17 18 19 20 21 29 30 31 32 1 2 3 4 U20 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128KX8 D7 D6 D5 D4 D3 D2 D1 D0 CS OE WE 27 26 23 22 11 10 7 6 5 28 12 D15_1 D14_1 D13_1 D12_1 D11_1 D10_1 D9_1 D8_1 CS0_1 RD_1 WR1_1 JP19 3 2 1
Confi guratio n Resistors
VCC VCC JP18 3 2 1 R250 R251 R252 R253 R254 R255 R256 R257 R175 R258 R259 R260 R261 R262 R263 R264 R265 R266 R267 R268 R269 R270 R271 R272 R273 R274 R275 R276 R277 R278 R279 R280 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K D31_1 D30_1 D29_1 D28_1 D27_1 D26_1 D25_1 D24_1 D23_1 D22_1 D21_1 D20_1 D19_1 D18_1 D17_1 D16_1 D15_1 D14_1 D13_1 D12_1 D11_1 D10_1 D9_1 D8_1 D7_1 D6_1 D5_1 D4_1 D3_1 D2_1 D1_1 D0_1
5 CS 28 OE WE 12
U1 A16_1 A15_1 A14_1 A13_1 A12_1 A11_1 A10_1 A9_1 A8_1 A7_1 A6_1 A5_1 A4_1 A3_1 A2_1 A1_1 A0_1 13 14 15 16 17 18 19 20 21 29 30 31 32 1 2 3 4 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128KX8 D7 D6 D5 D4 D3 D2 D1 D0 27 26 23 22 11 10 7 6 D23_1 D22_1 D21_1 D20_1 D19_1 D18_1 D17_1 D16_1 CS0_1 RD_1 WR2_1 A16_1 A15_1 A14_1 A13_1 A12_1 A11_1 A10_1 A9_1 A8_1 A7_1 A6_1 A5_1 A4_1 A3_1 A2_1 A1_1 A0_1 13 14 15 16 17 18 19 20 21 29 30 31 32 1 2 3 4
U2 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128KX8 D7 D6 D5 D4 D3 D2 D1 D0 CS OE WE 27 26 23 22 11 10 7 6 5 28 12 D7_1 D6_1 D5_1 D4_1 D3_1 D2_1 D1_1 D0_1 CS0_1 RD_1 WR0_1
5 CS 28 OE WE 12
VCC
R281 R282 U24 D7_1 D6_1 D5_1 D4_1 D3_1 D2_1 D1_1 D0_1 CS3_1 MEMCLK_1 RESET 10 9 8 7 6 5 4 3 14 13 11 D8 D7 D6 D5 D4 D3 D2 D1 CLKEN CLK CLR 74AC825SC Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 15 16 17 18 19 20 21 22 R283 R284 R285 R286 R287 R288
390R 390R 390R 390R 390R 390R 390R 390R
D19 D20 D21 D22 D23 D24 D25 D26
23 O C3 2 O C2 1 O C1
P M C- Sierra, Inc.
T itle
E thernet Division
Portlan d, OR. U.S.A. PM3351 2 Po rt Ref. Design - Memory 1
Size B Date: Document Number Monday, November 03, 1997 Sheet 7 of 9 Rev
D
38.3
VCC VCC
38.3
C22 .01uF R28 C23 C32 82.5 82.5 82.5 82.5 82.5 82.5 .1uF .1uF T1 PE68515 R36 25 24 20 21 15 16 130 130 130 130 130 130 2 1 R33 R50 10.5 10.5 Receive 1 2 3 U7 PMRD+ PMRDDP83223 TWISTER 4.7K R56 R53 R29 R66 R51 R32 R73 17 19 12 18 6 VCC VCC R63 4.7K R69 R62 42 41 38 37 36 R72 R52 R54 680 D4 LED LED LED LED LED R12 Place Close To Pin !!! VCC PHY_RESET R290 4.7K R34 4.7K R49 511 Q3 NPN R19 C14 1% C17 1000pF 10.5 1000pF 10.5 47.5 47.5 1 2 3 4 5 6 7 8 50 50 50 50 RD+ RDT D+ T D680 D3 680 D5 680 D1 680 D2 23 13 26 EXT VCC VCC VCC EQSEL LBEN ENCSEL CDET T XREF 14 GND 22 GND 3 RXGND 28 RXGND 7 T XGND 10 T XGND 4 RXVCC 27 RXVCC 5 T XVCC 11 T XVCC C12 .01uF J1 RJ45S-X2 T XO+ T XO9 8 16 14 15 10 12 11 Common Mode Choke Isolation Xformer 7 5 6 R47 R55 R26 PMID+ PMIDSD+ SDRXI+ RXIVPECL_1 61 60 69 80 85 97 40 52 71 59 68 79 84 83 14 13 96 39 51 70 R31
4.7K
4.7K
4.7K
4.7K
4.7K
NC NC NC
RCLKGND IOGND4 IOGND5 IOGND6 REFGND
IOGND1 IOGND2 IOGND3 PCSGND
IOVCC4 IOVCC5 IOVCC6 REFVCC
IOVCC1 IOVCC2 IOVCC3 PCSVCC
R5
R79
R64
R8
R15
4.7K
R21
4.7K
R13
R65
T XCLK_1 T XD3_1 T XD2_1 T XD1_1 T XD0_1 T XEN_1 CRS_1 COL_1 RXCLK_1 RXER_1 RXDV_1 RXD3_1 RXD2_1 RXD1_1 RXD0_1 MDC_1 MDIO_1 R67 R7 R16 R78 R77 R76 R71 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
82 75 76 77 78 74 73 66 65 62 63 64 55 56 57 58 43 72 67 95 46 47 98 99 100 1 86 81 2 34 33
T X_CLK MII T XD3 INTERFACE T XD2 T XD1 T XD0 T X_EN T X_ER CRS/PHYAD2 COL RX_CLK RX_ER/PHYAD4 RX_DV RXD3 RXD2 RXD1 RXD0 RXEN MDC MDIO AN0 CFG INTERFACE AN1 REPEAT ER 10BT SER BPALIGN BP4B5B BPSCR REFIN CLK25M OSCIN X2 X1 CLOCK INTERFACE
100 Mb/s INTERFACE U6 DP83840A 10/100Mb/s ETHERNET PHY
RD+ RDSD+ SDT D+ T DLBEN/PHYAD0 ENCSEL/PHYAD1
5 6 8 7 17 16 49 53
R61
Isolation Xformer
10 Mb/s INTERFACE
21 RXI+ 20 RXI- 26 T XU+ 25 T XU- 24 T XS+ 23 T XS- 29 REQ 28 RT X T D0 T D1 T RST T CLK T MS LED1 LED2 LED3 LED4 LED5 50 91 92 93 94
Common Mode Choke Transmit
Auto Xformer
R4 R3
4.7K 4.7K
JTAG INTERFACE
LED INTERFACE
SY SCLK_1
VCC R20 4.7K
CGMGND CRMGND ANAGND
CRMVCC ECLVCC CGMVCC
RES_0(4) RES_0(3) RES_0(2) RES_0(1)
ANAVCC PLLVCC
OGND PLLGND T DGND RXGND
OVCC T DVCC RXVCC
R70 R68 4.7K 4.7K
Q2 NPN
R18
Q1 NPN
R11 10.5
C13 1000pF R17 R23 R14 R9
VCC 4 45 90 48 9 31 35 30 27 19 12 15 87 32 22 18 88 11 10 R25 VPECL_1 R24 4.7K 4.7K C18 9pF 75 75
Chassis Ground 50 50
R35
VCC
Ferrite Bead FB4 1 2 R74 4 C55 .01uF C54 22uF
VCC
Ferrite Bead FB3 1 2 C49 .01uF C48 .01uF C38 .1uF C36 .1uF C51 .1uF C52 22uF C50 22uF 1
Ferrite Bead FB2 2 C33
VA_1 C34 C35 .1uF C37 .1uF C46 22uF C21 .001uF 2KV
.01uF .01uF
VCC
Ferrite Bead FB1 1 2 R6 10 C15 .01uF C8 22uF
P M C- Sierra, Inc.
T itle Size B Date:
R48
R30
Portlan d, OR. U.S.A. PM 3351 2 Port Re f. Design - Phy 1
Document Number Monday, November 03, 1997 Sheet 8 of 9 Rev
R27
E thernet Division
SHIELD2 SHIELD1
R22
54 SPEED_10 89 SPD_100/PHYAD3 44 RESET 3 LOWPWR
D
VP
VP VCC
C104 + .1uF
C102 + .1uF
C125 + .1uF
C105 + .1uF
C108 + .1uF
C100 + .1uF
C89 + .1uF
C80 + .1uF
C43 + .1uF
C60 + .1uF
C63 + .1uF
C73 + .1uF
C72 + .1uF
C71 + .1uF
C70 + .1uF
C69 + C19 .01uF C67 .01uF C39 C20 C1 .1uF C47 .1uF C16 .1uF C78 .1uF C124 .1uF C101 .1uF C7 22uF C53 22uF .1uF .01uF .01uF
VP
VP VCC
C81 + .1uF
C82 + .1uF
C83 + .1uF
C122 + .1uF
C84 + .1uF
C126 + .1uF
C127 + .1uF
C128 + .1uF
C68 + .1uF
C64 + .1uF
C61 + .1uF
C58 + .1uF
C45 + .1uF
C44 + .1uF
C40 + .1uF
C27 + C114 .01uF C77 .01uF C134 C136 C10 .1uF C113 .1uF C99 .1uF C87 .1uF C41 .1uF C132 .1uF C79 22uF C145 22uF .1uF .01uF .01uF
VP
VP
C129 + .1uF
C130 + .1uF
C85 + .1uF
C121 + .1uF
C107 + .1uF
C90 + .1uF
C86 + 22uF
C131 + 22uF
C28 + .1uF
C29 + .1uF
C30 + .1uF
C31 + .1uF
C26 + .1uF
C57 + .1uF
C25 + 22uF
C66 + 22uF
VCC * Case tab is to be connected to VP plane (pin2)
C4 + .1uF
C59 + .1uF
C5 + .1uF
C6 + .1uF
C3 + .1uF
C2 + .1uF
C56 + .1uF
C9 + .1uF
C91 + .1uF
C149 + .1uF
C11 + .1uF
C65 + .1uF
U18 LT 1585CT -3.3-ND 4.6A
VCC
VCC GND VP
JK1 VP VCC 1 VCC
1 C167 2200uF ALUMINUM ELECT
3 1 2
+ VCC JK2 + C103 + .1uF .1uF C142 + .1uF C75 + .1uF C42 + .1uF C76 + .1uF C146 + .1uF C106 + .1uF C109 + .1uF C24 + .1uF C62 + .1uF C74 + .1uF C88 + .1uF C150 + C143 10uF T ANT + C144 10uF T ANT 1 GND 1
VCC
C155
C156
C157
C158
C159
C160
C161
C162
C163
C164
C165
+
+
+
+
+
+
+
+
+
+
+
C166
P M C- Sierra, Inc.
+ T itle
E thernet Division
Portlan d, OR. U.S.A. PM 3351 2 P ort Re f. Design - Power
Size B Date: Document Number Monday, November 03, 1997 Sheet 9 of 9 Rev
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
22uF
22uF
D
PMC-Sierra, Inc. REFERENCE DESIGN
PMC-970390 ISSUE 1 ADVANCE
PM3351 ELAN 1x100
2-PORT 10/100 MBIT/S ETHERNET SWITCH
CONTACTING PMC-SIERRA PMC-Sierra, Inc. Ethernet Products Division 9400 SW Gemini Dr. Beaverton, OR 97008 Telephone: 503 520-1800 Facsimile: 503 520-1700 Document Information: Product Information: Applications information: Web Site: document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
____________________________________________________________________________________________
Seller will have no obligation or liability in respect of defects or damage caused by unauthorized use, mis-use, accident, external cause, installation error, or normal wear and tear. There are no warranties, representations or guarantees of any kind, either express or implied by law or custom, regarding the product or its performance, including those regarding quality, merchantability, fitness for purpose, condition, design, title, infringement of thirdparty rights, or conformance with sample. Seller shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained in this document. In no event will Seller be liable to Buyer or to any other party for loss of profits, loss of savings, or punitive, exemplary, incidental, consequential or special damages, even if Seller has knowledge of the possibility of such potential loss or damage and even if caused by Seller's negligence. (c) 1998 PMC-Sierra, Inc. PMC-970390 Issue 1 Printed in USA Issue date: April 1998
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

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